 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| general description the MAX17409 is a 1-phase quick-pwm? step-down vid power-supply controller for nvidia ? graphics power. the quick-pwm control provides instantaneous response to fast-load current steps. active voltage positioning reduces power dissipation and bulk output capacitance requirements and allows ideal positioning compensation for tantalum, polymer, or ceramic bulk output capacitors. the MAX17409 is intended for two different notebook processor core applications: either bucking down the bat- tery directly to create the core voltage, or bucking down the +5v system supply. the single-stage conversion method allows this device to directly step down high-volt- age batteries for the highest possible efficiency. alternatively, 2-stage conversion (stepping down the +5v system supply instead of the battery) at higher switching frequency provides the minimum possible physical size. a slew-rate controller allows controlled transitions between vid codes. a thermistor-based temperature sensor provides programmable thermal protection. the MAX17409 is available in a 28-pin, 4mm x 4mm tqfn package. applications nvidia gpu core power supplies voltage-positioned step-down converters 2-to-4 li+ cells battery to processor core supply converters notebooks/desktops/servers features 1-phase quick-pwm controller ?mv v out accuracy over line, load, and temperature 6-bit graphics dac (12.5mv lsb) active voltage positioning with adjustable gain accurate droop and current limit remote output and ground sense buffered 2v reference output for offsets power-good window comparator temperature comparator drives large synchronous rectifier fets 2v to 26v power input range adjustable switching frequency (600khz max) output overvoltage and undervoltage protection soft-startup and soft-shutdown internal boost diodes MAX17409 1-phase quick-pwm nvidia cpu controller ________________________________________________________________ maxim integrated products 1 26 27 25 24 10 9 11 gnds/ofsp csn csp skip thrm 12 imon bst dl pgnd lx g5 g4 12 ref 4567 20 21 19 17 16 15 ilim v cc g1 g0 shdn pwrgd MAX17409 pad gnd fb v dd 3 18 28 8 ccv ton vrhot 23 13 g2 gnd 22 14 g3 dh thin qfn top view pin configuration ordering information 19-4590; rev 0; 4/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. part temp range pin-package MAX17409gti+ -40c to +105c 28 tqfn-ep* quick-pwm is a trademark of maxim integrated products, inc. nvidia is a registered trademark of nvidia corp.
MAX17409 1-phase quick-pwm nvidia cpu controller 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1, v in = 12v, v dd = v cc = 5v, shdn = ilim = v cc , skip = gnds = pgnd = gnd, v fb = v csp = v csn = 1.05v; g5Cg0 set for 1.05v (g0Cg5 = 100110); t a = 0 c to +85 c , unless otherwise specified. typical values are at t a = +25c.) (note 3) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc , v dd to gnd .....................................................-0.3v to +6v g0Cg5 to gnd .........................................................-0.3v to +6v csp, csn to gnd ....................................................-0.3v to +6v ilim, thrm, vrhot , pwrgd to gnd ....................-0.3v to +6v skip to gnd.............................................................-0.3v to +6v ccv, fb, imon, ref to gnd .....................-0.3v to (v cc + 0.3v) shdn to gnd (note 1)...........................................-0.3v to +30v ton to gnd ...........................................................-0.3v to +30v gnds/ofsp, pgnd to gnd (note 2) ...................-0.3v to +0.3v internal driver (note 2) dl to pgnd .............................................-0.3v to (v dd + 0.3v) bst to gnd .........................................................-0.3v to +36v lx to bst...............................................................-6v to +0.3v bst to v dd ..........................................................-0.3v to +30v dh to lx .................................................-0.3v to (v bst + 0.3v) continuous power dissipation (t a = +70c) 28-pin 4mm x 4mm tqfn (derate 21.3mw/c above +70c) ............................1702mw operating temperature range .........................-40c to +105c junction temperature ......................................................+150c storage temperature range .............................-65c to +165c lead temperature (soldering, 10s) .................................+300c parameter symbol conditions min typ max units pwm controller input voltage range v cc , v dd 4.5 5.5 v dc output-voltage accuracy measured at fb with respect to gnds; includes load-regulation error (note 4) -6 +6 mv line regulation error v cc = 4.5v to 5.5v, v in = 4.5v to 26v 0.1 % gnds input range -200 +200 mv gnds/ofsp gain a gnds v out / v gnds , -200mv v gnds +200mv 0.97 1.00 1.03 v/v gnds/ofsp input bias current i gnds -2 +2 a v cc = 4.5v to 5.5v, i ref = 100a 1.98 2.000 2.02 ref voltage v ref i ref = 0 to 1ma 1.97 2.000 2.02 v dynamic vid slew-rate accuracy 11.0 12.5 14.0 mv/s soft-start/soft-shutdown slew-rate accuracy 1.248 1.56 1.872 mv/s r ton = 96.75k 142 167 192 r ton = 200k 300 333 366 on-time (note 5) t on v in = 12v, v fb = 1.2v r ton = 303.25k 425 500 575 ns minimum off-time t off(min) measured at dh (note 5) 300 375 ns ton shutdown input current shdn = gnd, v in = 26v, v cc = v dd = 0 or 5v 0.01 0.1 a note 1: shdn might be forced to 12v for the purpose of debugging prototype breadboards using the no-fault test mode, which dis- ables fault protection. note 2: measurements valid using a 20mhz bandwidth limit. MAX17409 1-phase quick-pwm nvidia cpu controller _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units bias currents quiescent supply current (v cc ) i cc measured at v cc , skip = 5v, fb forced above the regulation point 1.5 3 ma quiescent supply current (v dd ) i dd measured at v dd , skip = 0v, fb forced above the regulation point, t a = +25c 0.02 1 a shutdown supply current (v cc ) measured at v cc , shdn = gnd, t a = +25c 0.01 1 a shutdown supply current (v dd ) measured at v dd , shdn = gnd, t a = +25c 0.01 1 a fault protection skip mode after output reaches the regulation voltage or pwm mode; measured at fb with respect to unloaded output voltage 250 300 350 mv soft-start, soft-shutdown, skip mode, and output have not reached the regulation voltage; measured at fb 1.45 1.50 1.55 output overvoltage protection threshold v ovp minimum ovp threshold; measured at fb 0.8 v output overvoltage propagation delay t ovp fb forced 25mv above trip threshold 10 s output undervoltage protection threshold v uvp measured at fb with respect to unloaded output voltage -450 -400 -350 mv output undervoltage propagation dela y t uvp fb forced 25mv below trip threshold 10 s pwrgd startup delay measured at startup from the time when shdn goes high 3 5 8 ms lower threshold, falling edge (undervoltage) -350 -300 -250 pwrgd threshold measured at fb with respect to unloaded output voltage, 15mv hysteresis (typ) upper threshold, rising edge (overvoltage) +150 +200 +250 mv pwrgd transition blanking time t blank measured from the time when fb reaches the target voltage (note 4) based on the slew rate 20 s pwrgd delay fb forced 25mv outside the pwrgd trip thresholds 10 s pwrgd output low voltage i sink = 3ma 0.4 v pwrgd leakage current high state, pwrgd forced to 5v 1 a v cc undervoltage-lockout threshold v uvlo(vcc) rising edge, 50mv typical hysteresis, controller disabled below this level 4.05 4.25 4.48 v csn discharge resistance in uvlo v cc = v dd = 4.0v 8 electrical characteristics (continued) (circuit of figure 1, v in = 12v, v dd = v cc = 5v, shdn = ilim = v cc , skip = gnds = pgnd = gnd, v fb = v csp = v csn = 1.05v; g5Cg0 set for 1.05v (g0Cg5 = 100110); t a = 0 c to +85 c , unless otherwise specified. typical values are at t a = +25c.) (note 3) electrical characteristics (continued) (circuit of figure 1, v in = 12v, v dd = v cc = 5v, shdn = ilim = v cc , skip = gnds = pgnd = gnd, v fb = v csp = v csn = 1.05v; g5Cg0 set for 1.05v (g0Cg5 = 100110); t a = 0 c to +85 c , unless otherwise specified. typical values are at t a = +25c.) (note 3) parameter symbol conditions min typ max units thermal comparator and protection vrhot trip threshold measured at thrm with respect to v cc ; falling edge; typical hysteresis = 100mv 29.2 30 30.8 % vrhot delay t vrhot thrm forced 25mv below the vrhot trip threshold; falling edge 10 s vrhot output on-resistance r vrhot low state 2 8 vrhot leakage current i vrhot high state, vrhot forced to 5v, t a = +25 c 1 a thrm input leakage i thrm v thrm = 0 to 5v, t a = +25 c -100 +100 na thermal-shutdown threshold t shdn typical hysteresis = 15 c 160 c valley current limit and droop v ref - v ilim = 100mv 7 10 13 current-limit threshold voltage (positive adjustable) v limit v csp - v csn v ref - v ilim = 500mv 45 50 55 mv current-limit threshold voltage (positive default) ilim = v cc , v csp - v csn 20 22.5 25 mv current-limit threshold voltage (negative) accuracy v limit(neg) v csp - v csn , nominally -125% of v limit -4 +4 mv current-limit threshold voltage (zero crossing) v zero v pgnd - v lx 1 mv csp, csn common-mode input range 0 1.9 v csp, csn input current t a = +25c -0.2 +0.2 a ilim input current t a = +25c -100 +100 na droop amplifier (gmd) offset (v csp - v csn ) at i fb = 0 -0.75 +0.75 mv droop amplifier (gmd) transconductance i fb / (v csp - v csn ); fb = csn = 0.45v to 2.0v, and (v csp - v csn ) = -15.0mv to +15.0mv 592 600 608 s gate drivers high state (pullup) 0.9 2.5 dh gate-driver on-resistance r on(dh) bst - lx forced to 5v low state (pulldown) 0.7 2.0 high state (pullup) 0.7 2.0 dl gate-driver on-resistance r on(dl) low state (pulldown) 0.25 0.7 dh gate-driver source current i dh(source) dh forced to 2.5v, bst - lx forced to 5v 2.2 a dh gate-driver sink current i dh(sink) dh forced to 2.5v, bst - lx forced to 5v 2.7 a dl gate-driver source current i dl(source) dl forced to 2.5v 2.7 a dl gate-driver sink current i dl(sink) dl forced to 2.5v 8 a internal bst switch on-resistance r bst i bst = 10ma, v dd = 5v 10 20 MAX17409 1-phase quick-pwm nvidia cpu controller 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 12v, v dd = v cc = 5v, shdn = ilim = v cc , skip = gnds = pgnd = gnd, v fb = v csp = v csn = 1.05v; g5Cg0 set for 1.05v (g0Cg5 = 100110); t a = 0 c to +85 c , unless otherwise specified. typical values are at t a = +25c.) (note 3) parameter symbol conditions min typ max units current monitor current-monitor transconductance g m(imon) i imon / (v csp - v csn ), v csn = 0.5v to 1.0v 4.9 5.0 51 ms current-monitor offset referred to v(csp,csn) i imon = 0 -1.0 +1.0 mv imon clamp voltage v imon i imon = -1.0ma 1.05 1.10 1.15 v logic and i/o logic-input high voltage v ih shdn , skip 2.3 v logic-input low voltage v il shdn , skip 1.0 v low-voltage logic-input high voltage v ihlv g0Cg5 0.67 v low-voltage logic-input low voltage v illv g0Cg5 0.33 v logic-input current t a = +25c, shdn , skip, g0Cg5 = 0 or 5v -1 +1 a MAX17409 1-phase quick-pwm nvidia cpu controller _______________________________________________________________________________________ 5 electrical characteristics (circuit of figure 1, v in = 12v, v dd = v cc = 5v, shdn = ilim = v cc , skip = gnds = pgnd = gnd, v fb = v csp = v csn = 1.05v; g5Cg0 set for 1.05v (g0Cg5 = 100110); t a = -40 c to +105 c , unless otherwise specified.) (note 3) parameter symbol conditions min typ max units pwm controller input voltage range v cc , v dd 4.5 5.5 v dc output-voltage accuracy measured at fb with respect to gnds, includes load regulation error (note 4) -10 +10 mv gnds input range for positive offset and remote-sense errors -200 +200 mv gnds/ofsp gain a gnds v out / v gnds , -200mv v gnds +200mv 0.95 1.05 v/v v cc = 4.5v to 5.5v, i ref = 100a 1.97 2.03 ref voltage v ref i ref = 0 to 1ma 1.95 2.03 v dynamic vid slew-rate accuracy 10 15 mv/s soft-start/soft-shutdown slew-rate accuracy 1.248 1.872 mv/s r ton = 96.75k 142 192 r ton = 200k 300 366 on-time (note 5) t on v in = 12v, v fb = 1.2v r ton = 303.25k 425 575 ns minimum off-time t off(min) measured at dh (note 5) 400 ns bias currents quiescent supply current (v cc ) i cc measured at v cc , skip = 5v, fb forced above the regulation point 3 ma MAX17409 1-phase quick-pwm nvidia cpu controller 6 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 12v, v dd = v cc = 5v, shdn = ilim = v cc , skip = gnds = pgnd = gnd, v fb = v csp = v csn = 1.05v; g5Cg0 set for 1.05v (g0Cg5 = 100110); t a = -40 c to +105 c , unless otherwise specified.) (note 3) parameter symbol conditions min typ max units fault protection skip mode after output reaches the regulation voltage or pwm mode; measured at fb with respect to unloaded output voltage 250 350 mv output overvoltage-protection threshold v ovp soft-start, soft-shutdown, skip mode, and output have not reached the regulation voltage, measured at fb 1.45 1.55 v output undervoltage-protection threshold v uvp measured at fb with respect to unloaded output voltage -450 -350 mv pwrgd startup delay measured at startup from the time when shdn goes high 3 8 ms lower threshold, falling edge (undervoltage) -350 -250 mv pwrgd threshold measured at fb with respect to unloaded output voltage; 15mv hysteresis (typ) upper threshold, rising edge (overvoltage) +150 +250 mv pwrgd output low voltage i sink = 3ma 0.4 v v cc undervoltage-lockout threshold v uvlo(vcc) rising edge, 50mv typical hysteresis, controller disabled below this level 4.0 4.5 v thermal comparator and protection vrhot trip threshold measured at thrm with respect to v cc ; falling edge; typical hysteresis = 100mv 29.2 30.8 % vrhot output on-resistance r vrhot low state 8 valley current limit and droop v ref - v ilim = 100mv 7 13 current-limit threshold voltage (positive adjustable) v limit v csp - v csn v ref - v ilim = 500mv 45 55 mv current-limit threshold voltage (positive default) ilim = v cc , v csp - v csn 20 25 mv current-limit threshold voltage (negative) accuracy v limit(neg) v csp - v csn , nominally -125% of v limit -5 +5 mv csp, csn common-mode input range 0 1.9 v droop amplifier gmd) offset (v csp - v csn ) at i fb = 0 -1.0 +1.0 mv droop amplifier (gmd) transconductance i fb / (v csp - v csn ); fb = csn = 0.45v to 2.0v, and (v csp - v csn ) = -15.0mv to +15.0mv 588 612 s MAX17409 1-phase quick-pwm nvidia cpu controller _______________________________________________________________________________________ 7 electrical characteristics (continued) (circuit of figure 1, v in = 12v, v dd = v cc = 5v, shdn = ilim = v cc , skip = gnds = pgnd = gnd, v fb = v csp = v csn = 1.05v; g5Cg0 set for 1.05v (g0Cg5 = 100110); t a = -40 c to +105 c , unless otherwise specified.) (note 3) parameter symbol conditions min typ max units gate drivers high state (pullup) 2.5 dh gate-driver on-resistance r on(dh) bst - lx forced to 5v low state (pulldown) 2.0 high state (pullup) 2.0 dl gate-driver on-resistance r on(dl) low state (pulldown) 0.7 internal bst switch on-resistance r bst i bst = 10ma, v dd = 5v 20 current monitor current-monitor transconductance g m(imon) i imon / (v csp - v csn ) v csn = 0.5v to 1.0v 4.9 5.1 ms current-monitor offset referred to v(csp,csn) i imon = 0 -1.0 +1.0 mv imon clamp voltage v imon i imon = -1.0ma 1.05 1.15 v logic and i/o logic-input high voltage v ih shdn , skip 2.3 v logic-input low voltage v il shdn , skip 1.0 v low-voltage logic-input high voltage v ihlv g0Cg5 0.67 v low-voltage logic-input low voltage v illv g0Cg5 0.33 v note 3: limits are 100% production tested at t a = +25c. maximum and minimum limits over temperature are guaranteed by design and characterization. note 4: the equation for the target voltage v target is: v target = the slew-rate-controlled version of v dac , where v dac = 0 for shutdown, v dac = v vid otherwise (the v vid volt- ages for all possible vid codes are given in table 4). in pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load. note 5: on-time and minimum off-time specifications are measured from 50% to 50% at the dh pin, with lx forced to 0v, bst forced to 5v, and a 500pf capacitor from dh to lx to simulate external mosfet gate capacitance. actual in-circuit times might be different due to mosfet switching speeds. MAX17409 1-phase quick-pwm nvidia cpu controller 8 _______________________________________________________________________________________ 0.9v output efficiency vs. load current MAX17409 toc01 load current (a) efficiency (%) 10 1 0.1 50 60 70 80 90 100 40 0.01 100 20v skip mode pwm mode 7v 12v 0.9v output voltage vs. load current MAX17409 toc02 load current (a) output voltage (v) 12 14 10 8 6 4 2 0.89 0.90 0.91 0.92 0.88 016 skip mode pwm mode switching frequency vs. load current MAX17409 toc03 load current (a) switching frequency (khz) 10 1 0.1 100 50 150 200 250 300 350 0 0.01 100 v in = 12v skip mode pwm mode no-load supply current vs. input voltage MAX17409 toc04 input voltage (v) switching frequency (khz) 12 13 11 10 9 8 7 6 0.1 1 10 100 0.01 514 i in i in i cc + i dd i cc + i dd skip mode pwm mode 0.8125v output voltage distribution MAX17409 toc05 output voltage (v) sample percentage (%) 80 70 60 50 40 30 20 10 90 0 sample size = 100 +85 c +25 c 0.8085 0.8095 0.8105 0.8115 0.8125 0.8135 0.8145 0.8155 0.8165 0.8175 0.8075 gm (fb) transconductance distribution MAX17409 toc06 transconductance ( s) sample percentage (%) 45 40 35 30 25 20 15 5 10 50 0 sample size = 100 +85 c +25 c 592 594 596 598 600 602 604 606 608 610 590 typical operating characteristics (circuit of figure 1, v in = 12v, v cc = v dd = 5v, shdn = v cc , g0Cg5 set for 1.05v (g0Cg5 = 100110), t a = +25 c, unless other- wise specified.) MAX17409 1-phase quick-pwm nvidia cpu controller _______________________________________________________________________________________ 9 gm (imon) transconductance distribution MAX17409 toc07 transconductance (ms) sample percentage (%) 90 80 70 60 50 40 30 10 20 100 0 sample size = 100 +85 c +25 c 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10 4.90 soft-start waveform MAX17409 toc08 1ms/div a. shdn, 5v/div b. i lx , 10a/div c. v out , 500mv/div 0 0 0 0 0 e d c b a 5v 0.95v d. pwrgd, 5v/div e. dl, 5v/div i out = 0a, skip mode soft-shutdown waveform MAX17409 toc09 100 s/div a. shdn, 5v/div b. i lx , 10a/div c. v out , 500mv/div 0 0 0 0 0 e d c b a 5v 0.95v d. pwrgd, 5v/div e. dl, 5v/div i out = 0a, skip mode load-transient response (pwm mode) MAX17409 toc10 20 s/div a. v out , 50mv/div b. i lx , 20a/div 1a 0 c b a 0.95v c. lx, 10v/div i out = 1a - 11a load-transient response (skip mode) MAX17409 toc11 20 s/div a. v out , 50mv/div b. i lx , 20a/div 1a 0 c b a 0.95v c. lx, 10v/div i out = 1a - 11a typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v cc = v dd = 5v, shdn = v cc , g0Cg5 set for 1.05v (g0Cg5 = 100110), t a = +25 c, unless other- wise specified.) MAX17409 1-phase quick-pwm nvidia cpu controller 10 ______________________________________________________________________________________ pin description pin name function 1 imon current monitor output. the MAX17409 imon output sources a current that is directly proportional to the current-sense voltage as defined by: i imon = g m(imon) x (v csp - v csn ) where g m(imon) = 5ms (typ). the imon current is unidirectional (sources current out of imon only) for positive current-sense values. for negative current-sense voltages, the imon current is zero. connect an external resistor between imon and gnds to create the desired imon gain based on the following equation: r imon = 1.0v/(i load(max) x r sense x g m(imon) ) where i load(max) is the maximum load current, and r sense is the current-sense voltage. the imon voltage is internally clamped to 1.1v. the transconductance amplifier and voltage clamp are internally compensated, so imon cannot drive large external capacitance values. to filter the imon signal, use an rc filter as shown in figure 1. 2 gnds/ofsp remote ground-sense input/positive offset input. connect directly to the ground-sense pin or ground connection of the load. gnds internally connects to a transconductance amplifier that adjusts the feedback voltagecompensating for voltage drops between the regulators ground and the processors ground. 3 fb remote-sense feedback input and voltage-positioning transconductance amplifier output. connect resistor r fb between fb and the output remote-sense pin (or kelvin-sensed to the supply pin of the load) for best accuracy and to set the steady-state droop based on the voltage- positioning gain requirement: r fb = r droop /(r sense x g md ) where r droop_dc is the desired voltage-positioning slope, g md = 600s (typ), and r sense is the current-sense resistance with respect to csp to csn current-sense inputs. see the current sense section for details on designing with sense resistors or inductor dcr sensing. shorting fb directly to the output effectively disables voltage positioning, but impacts the stability requirements. designs that disable voltage positioning require a higher minimum output capacitance esr to maintain stability (see the output capacitor selection section). fb enters a high-impedance state in shutdown. 4 csn negative inductor current-sense input. connect csn to the negative terminal of the inductor current-sensing resistor or directly to the negative terminal of the inductor if the lossless dcr sensing method is used (see figure 3). 5 csp positive inductor current-sense input. connect csp to the positive terminal of the inductor current- sensing resistor or directly to the positive terminal of the filtering capacitor used when the lossless dcr sensing method is used (see figure 3). 6 skip pulse-skipping control input. the skip signal indicates the power usage and sets the operating mode of the MAX17409. when the system forces skip high, the MAX17409 immediately enters automatic pulse-skipping mode. the controller returns to continuous forced-pwm mode when skip is pulled low and the output is in regulation. skip determines the operating mode and output- voltage transition slew rate as shown in the truth table below: skip functionality 0 normal slew rate, forced-pwm mode 1 normal slew rate, skip mode the skip state is ignored during soft-start and shutdown. the MAX17409 always uses pulse- skipping mode during startup to ensure a monotonic power-up. during shutdown, the controller always uses forced-pwm mode so the output can be actively discharged. MAX17409 1-phase quick-pwm nvidia cpu controller ______________________________________________________________________________________ 11 pin description (continued) pin name function 7 thrm comparator input for thermal protection. thrm connects to the positive input of an internal comparator. the comparators negative input connects to an internal resistive voltage-divider that accurately sets the thrm threshold to 30% of the v cc voltage. connect the output of a resistor- divider and thermistor-divider (between v cc and gnd) to thrm with the values selected so the voltage at thrm falls below 30% of v cc (1.5v when v cc = 5v) at the desired high temperature. 8 ton switching frequency-setting input. an external resistor (r ton ) between the input power source and ton sets the switching frequency (f sw = 1/t sw ) according to the following equation used to determine the nominal switching period: t sw = 16.3pf x (r ton + 6.5k ) ton enters a high impedance in shutdown to reduce the input quies cent current. if the ton current is less than 10a, the MAX17409 disables the controller, sets the ton open fault latch, and pulls dh and dl low. 9 pwrgd open-drain power-good output. the MAX17409 forces pwrgd low when shdn is pulled low. after the controller is properly powered up, pwrgd becomes a high-impedance output as long as the feedback voltage is in regulation and the startup blanking time has expired. pwrgd becomes active 5ms after the MAX17409 reaches the vid target. the MAX17409 pulls pwrgd low when shutdown ( shdn = gnd) is pulled low, during startup, and during shutdown transitions. the pwrgd upper threshold is blanked during any downward output-voltage transition that occurs when the MAX17409 is in skip mode (skip = v cc ). pwrgd remains blanked until the transition- related pwrgd blanking period expires and the controller detects the output is in regulation (error- amplifier edge occurs). note: the pullup resist ance on pwrgd causes additional shutdown current. 10 shdn shutdown control input. connect to v cc for normal operation. connect to ground to put the controller into the low-power 1a (max) shutdown state. during startup, the controller ramps up the output voltage with a 1.56mv/s slew rate to the selected target voltage. during the shutdown transition, the MAX17409 softly ramps down the output voltage with a 1.56mv/s slew rate. forcing shdn to 11v ~ 13v disables overvoltage protection, undervoltage protection, and thermal shutdown, and clears the fault latches. 11C16 g0Cg5 low-voltage (1.0v logic) vid dac code inputs. the g0Cg5 inputs do not have internal pullups. these 1.0v logic inputs are designed to interface directly with the p. the output voltage is set by the dac code indicated by the logic-level voltages on g0Cg5. 17 pgnd power ground. ground connection for the dl driver. 18 dl low-side gate-driver output. dl swings from v dd to pgnd. dl is forced low in shutdown. dl is also forced low when an output overvoltage fault is detected, overriding any negative current-limit condition that might be present. dl is forced low in skip mode after detecting an inductor current zero crossing. 19 v dd driver-supply voltage input. v dd supplies power to the low-side gate driver (dl) and to the internal bst switch used to refresh the bst capacitor. connect v dd to the 4.5v to 5.5v system supply voltage. bypass v dd to pgnd with a 1f or greater ceramic capacitor. 20 bst boost flying capacitor connection. bst provides the upper supply rail for the dh high-side gate driver. an internal switch between v dd and bst charges the flying capacitor while the low-side mosfet is on (dl pulled high and lx pulled to ground). 21 lx inductor connection. lx serves as the lower supply rail for the dh high-side gate driver. the MAX17409 also uses lx as the input to the zero-crossing comparator. MAX17409 1-phase quick-pwm nvidia cpu controller 12 ______________________________________________________________________________________ pin description (continued) pin name function 22 dh high-side gate-driver output. dh swings from lx to bst. the controller pulls dh low in shutdown. 23 gnd analog ground. internally connected to gnd. 24 vrhot thermal comparators open-drain output. the comparator pulls vrhot low when the voltage at thrm drops below 30% of v cc (1.5v with 5v v cc ). vrhot is high impedance in shutdown. 25 ref buffered 2v reference output. bypass ref with a 100pf to 1000pf capacitor. do not exceed 1000pf. 26 ilim valley current-limit adjustment input. the valley current-limit threshold voltage at csp to csn equals precisely 1/10 of the differential ref to ilim voltage over a 0.1v to 0.5v range (10mv to 50mv current-sense range). the negative current-limit threshold is nominally -125% of the corresponding valley current-limit threshold. connect ilim directly to v cc to set the default 22.5mv current-limit threshold setting. 27 v cc analog supply voltage. connect to a 4.5v to 5.5v source. bypass to gnd with a 1f minimum capacitor. 28 ccv integrator capacitor connection. connect a capacitor (c ccv ) from ccv to gnd to set the integration time constant. choose the capacitor value according to: 16 x [c ccv /g m(ccv) ] x f sw >> 1 where g m(ccv) = 320 s (max) is the integrators transconductance and f sw is the switching frequency set by the r ton resistance. the integrator is internally disabled during any downward output-voltage transition that occurs in pulse-skipping mode, and remains disabled until the transition blanking period expires and the output reaches regulation (error-amplifier transition detected). ep exposed pad (backside). internally connected to the substrate. connect to the gr ound plane through a thermally enhanced via. MAX17409 1-phase quick-pwm nvidia cpu controller ______________________________________________________________________________________ 13 output sense ground sense pwrgd g0 g1 g2 g3 g4 vid inputs shdn on off ref gnds/ofsp v ref 3.3v (vron) core output input 7v to 24v l1 5v bias input lx dh dl bst pgnd csp csn imon agnd ton fb vrhot v cc c1 1.0 f agnd pwr pwr r ton r bst 0 c bst 0.1 f c in n hi r10 r11 c7 r fb c8 1000pf r gnd 0 r13 10 r16 10 r15 10 r14 10 r1 10 c2 1.0 f switching frequency (f sw = 1/t sw ): t sw = 16.3pf x (r ton + 6.5k ) valley current limit set by the time to ilim v limit = 0.2v x r2/(r2 + r3) slew rate set by time bias current dv/dt = 12.5mv/ s x 71.5k /(r2 + r3) load line adjustment: r fb = r droop /(r sense x 600 s) v dd r imon ilim r3 r2 r4 10k gnd (ep) g5 d1 11 12 13 14 15 16 10 25 26 9 24 1 3 2 4 5 23 17 18 21 22 20 8 19 27 n lo ntc1 dcr thermal compensation remote-sense filters catch resistors required when cpu not populated c out r5 10k r8 10k MAX17409 pwr pwr pwr skip 6 c5 open agnd agnd c ref 100pf c6 open c3 r20 open agnd c ccv 100pf ccv 28 agnd agnd agnd agnd pwr c9 1000pf v ref thrm v cc ntc2 100k b = 4700 7 r6 7.87k agnd c4 0.1 f agnd figure 1. MAX17409 application circuit MAX17409 1-phase quick-pwm nvidia cpu controller 14 ______________________________________________________________________________________ s r q r s q trig q one-shot pgnd skip dl bst dh lx ccv ton csp csn minimum off-time v cc gnd pwrgd target +200mv target -300mv target +300mv target -400mv ref (2.0v) shdn trig q on-time one shot fb v dd fb pgnd lx 1mv skip g m(ccv) g m(fb) g m(gnds) csp csn g0?g5 gnds dac slew control fault tar get ref ilim ref r 7r fault blank vrhot thrm 0.3 x v cc imon MAX17409 5ms startup delay figure 2. functional diagram MAX17409 1-phase quick-pwm nvidia cpu controller ______________________________________________________________________________________ 15 design parameters 14a design 9a design 5a design input voltage range 8v to 20v 8v to 20v 8v to 20v maximum load current 14a 9a 5a transient load current 10a 7a 4a components ton resistance (r ton ) 200k (f sw = 300khz) 170k (f sw = 350khz) 150k (f sw = 390khz) inductance (l1) 0.6h, 17a, 2.3m nec-tokin mpc0750lr60c 0.75h, 10.7a, 6.2m toko fdve0630-r75m 1.50h, 8a, 12.1m toko fdve0630-1r5m high-side mosfet (n hi ) 9.4m /12.0m (typ/max) fairchild fds6298 11m /13.75m (typ/max) vishay si7392dp 14.5m /20.5m (typ/max) international rectifier irf7904 low-side mosfet (n lo ) 4.2m /5.0m (typ/max) fairchild fds8670 5m /6.5m (typ/max) international rectifier irf7822 10m /13m (typ/max) international rectifier irf7904 output capacitors (c out ) 1x 470f, 6m , 2v sanyo 2tpe470m6 1x 330f, 6m , 2v sanyo 2tpe330m6 1x 220f, 6m , 2v sanyo 2tpe220m6 input capacitors (c in ) 2x 10f, 25v ceramic (1210) 1x 10f, 25v ceramic (1210) 1x 10f, 25v ceramic (1210) ref/ilim resistance (r2) 10k 17.8k 20k ilim/gnd resistance (r3) 63.4k 60.4k 54.9k fb resistance (r fb ) 100 100 100 feedforward capacitance (c3) 0.22f 0.15f 0.1f lx/csp resistance (r10) 1.3k 1.3k 1.3k csp/csn series resistance (r11 + ntc1) 2k + 10k ntc (b = 3380) 2k + 10k ntc (b = 3380) 2k + 10 ntc (b = 3380) dcr sense capacitance (c7) 0.22f, 6v ceramic (0603) 0.1f, 6v ceramic (0603) 0.1f, 6v ceramic (0603) imon resistance (r imon ) 6.81k 3.92k 3.24k table 1. component selection for standard applications manufacturer website avx corporation www.avxcorp.com fairchild semiconductor www.fairchildsemi.com nec-tokin america, inc. www.nec-tokinamerica.com panasonic corp. www.panasonic.com sanyo electric co., ltd. www.sanyodevice.com manufacturer website taiyo yuden www.t-yuden.com tdk corp. www.component.tdk.com toko america, inc. www.tokoam.com toshiba america electronic components, inc. www.toshiba.com/taec vishay www.vishay.com table 2. component suppliers MAX17409 1-phase quick-pwm nvidia cpu controller 16 ______________________________________________________________________________________ detailed description free-running, constant on-time pwm controller with input feed-forward the quick-pwm control architecture is a pseudo-fixed- frequency, constant-on-time, current-mode regulator with voltage feed-forward (figure 2). this architecture relies on the output filter capacitors esr to act as the current-sense resistor, so the output ripple voltage pro- vides the pwm ramp signal. the control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to input voltage, and directly proportional to output volt- age (see the on-time one-shot section). another one- shot sets a minimum off-time. the on-time one-shot triggers when the error comparator goes low, the induc- tor current is below the valley current-limit threshold, and the minimum off-time one-shot times out. +5v bias supply (v cc and v dd ) the quick-pwm controller requires an external +5v bias supply in addition to the battery. typically, this +5v bias supply is the notebooks 95% efficient +5v system supply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associat- ed with the +5v linear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. if stand-alone capability is needed, the +5v bias supply can be generated with an external linear regulator. the +5v bias supply must provide v cc (pwm con- troller) and v dd (gate-drive power), so the maximum current drawn is: where i cc is provided in the electrical characteristics table, f sw is the switching frequency, and q g(low) and q g(high) are the mosfet data sheets total gate- charge specification limits at v gs = 5v. v in and v dd can be connected together if the input power source is a fixed +4.5v to +5.5v supply. if the +5v bias supply is powered up prior to the battery sup- ply, the enable signal ( shdn going from low to high) must be delayed until the battery voltage is present to ensure startup. switching frequency (ton) connect a resistor (r ton ) between ton and v in to set the switching period (t sw = 1/f sw ): t sw = 16.3pf x (r ton + 6.5k ) a 96.75k to 303.25k corresponds to switching peri- ods of 167ns (600khz) to 500ns (200khz), respectively. high-frequency (600khz) operation optimizes the appli- cation for the smallest component size, trading off effi- ciency due to higher switching losses. this might be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. low-frequency (200khz) opera- tion offers the best overall efficiency at the expense of component size and board space. on-time one-shot the core contains a fast, low-jitter, adjustable one-shot that sets the high-side mosfets on-time. the one-shot varies the on-time in response to the input and feed- back voltages. the main high-side switch on-time is inversely proportional to the input voltage as measured by the r ton input, and proportional to the feedback voltage (v fb ): where the switching period (t sw = 1/f sw ) is set by the resistor at the ton pin and 0.075v is an approximation to accommodate the expected drop across the low- side mosfet switch. this algorithm results in a nearly constant switching fre- quency and balanced inductor currents despite the lack of a fixed-frequency clock generator. the benefits of a constant switching frequency are twofold: first, the fre- quency can be selected to avoid noise-sensitive regions such as the 455khz if band; second, the induc- tor ripple-current operating point remains relatively con- stant, resulting in easy design methodology and predictable output-voltage ripple. the on-time one- shots have good accuracy at the operating points specified in the electrical characteristics table. on- times at operating points far removed from the condi- tions specified in the electrical characteristics table can vary over a wider range. on-times translate only roughly to switching frequen- cies. the on-times guaranteed in the electrical characteristics table are influenced by switching delays in the external high-side mosfet. resistive losses, including the inductor, both mosfets, output capacitor esr, and pcb copper losses in the output and ground tend to raise the switching frequency at higher output currents. also, the dead-time effect increases the effective on-time, reducing the switching frequency. it occurs only during forced-pwm operation and dynamic output-voltage transitions when the induc- tor current reverses at light or negative load currents. with reversed inductor current, the inductors emf causes lx to go high earlier than normal, extending the t tv v v on main sw fb in () . = + () 0 075 iifq q bias cc sw g low g high =+ + () () ( ) MAX17409 1-phase quick-pwm nvidia cpu controller ______________________________________________________________________________________ 17 on-time by a period equal to the dh rising dead time. for loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pcb resistances; v drop2 is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and pcb resis- tances; and t on is the on-time as determined above. current sense the output current is differentially sensed by the high- impedance current-sense inputs (csp and csn). low- offset amplifiers are used for voltage-positioning gain, current-limit protection, and power monitoring. sensing the current at the output offers advantages, including less noise sensitivity and the flexibility to use either a current-sense resistor or the dc resistance of the out- put inductor. using the dc resistance (r dcr ) of the output inductor allows higher efficiency. in this configuration, the initial tolerance and temperature coefficient of the inductors dcr must be accounted for in the output-voltage droop- error budget and power monitor. this current-sense method uses an rc filtering network to extract the cur- rent information from the inductor (see figure 3). the resistive divider used should provide a current-sense resistance (r cs ) low enough to meet the current-limit requirements, and the time constant of the rc network should match the inductors time constant (l/r cs ): and: where r cs is the required current-sense resistance, and r dcr is the inductors series dc resistance. use the worst-case inductance and r dcr values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. to minimize the current-sense error due to the current- sense inputs bias current (i csp and i csn ), choose r1//r2 to be less than 2k and use the above equation to determine the sense capacitance (c eq ). choose capacitors with 5% tolerance and resistors with 1% tol- erance specifications. temperature compensation is recommended for this current-sense method. see the voltage positioning and loop compensation section. when using a current-sense resistor for accurate output- voltage positioning, the circuit requires a differential rc filter to eliminate the ac voltage step caused by the equivalent series inductance (l esl ) of the current-sense resistor (see figure 3). the esl-induced voltage step does not affect the average current-sense voltage, but results in a significant peak current-sense voltage error that results in unwanted offsets in the regulation voltage and results in early current-limit detection. similar to the inductor dcr sensing method above, the rc filters time constant should match the l/r time constant formed by the current-sense resistors parasitic inductance: where l esl is the equivalent series inductance of the current-sense resistor, r sense is the current-sense resis- tance value, c eq and r1 are the time-constant matching components. current limit the current-limit circuit employs a valley current- sensing algorithm that uses current-sense inputs (csp to csn) as the current-sensing elements. if the current- sense signal exceeds the current-limit threshold, the pwm controller does not initiate a new cycle until the inductor current drops below the valley current-limit threshold. since only the valley current level is actively limited, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple cur- rent. therefore, the exact current-limit characteristic and maximum load capability are a function of the cur- rent-sense resistance, inductor value, and battery volt- age. when combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. the positive current-limit threshold is fixed internally at 22.5mv (typ). there is also a negative current limit that prevents excessive reverse inductor currents when v out is sinking current. the negative current-limit threshold is 130% of the nominal valley current-limit threshold. when the inductor current drops below the negative current limit, the controller immediately acti- vates an on-time pulsedl turns off and dh turns on allowing the inductor current to remain above the negative current threshold. carefully observe the pcb layout guidelines to ensure that noise and dc errors do not corrupt the current-sense signals seen by the current-sense inputs (csp, csn). l r cr esl sense eq = 1 r l crr cs eq =+ ? ? ? ? ? ? 1 1 1 2 r r rr r cs dcr = + ? ? ? ? ? ? 2 12 f vv tvv v sw out drop on in drop drop = + () + () 1 12 - MAX17409 1-phase quick-pwm nvidia cpu controller 18 ______________________________________________________________________________________ sense resistor l MAX17409 c out input (v in ) c in csn csp pgnd dl dh lx c eq r1 n h n l d l l esl r sense c eq r1 = l sense r sense MAX17409 c out input (v in ) c in b) lossless inductor sensing for thermal compensation: r2 should consist of an ntc resistor in series with a standard thin-film resistor. csn csp pgnd dl dh lx c eq r 1 r 2 n h n l d l l inductor a) output series resistor sensing r dcr r cs = r2 r dcr r1 + r2 r dcr = l [ 1 + 1 ] c eq r1 r2 figure 3. current-sense methods feedback adjustment amplifiers voltage-positioning amplifier (steady-state dc droop) the MAX17409 includes a transconductance amplifier for adding gain to the voltage-positioning sense path. the amplifiers input is generated by the differential cur- rent-sense inputs, which sense the inductor current by measuring the voltage across either current-sense resistors or the inductors dcr. the amplifiers output connects directly to the regulators voltage-positioned feedback input (fb), so the resistance between fb and the output-voltage sense point determines the voltage- positioning gain: where the target voltage (v target ) is defined in the nominal output-voltage selection section, and the fb amplifiers output current (i fb ) is determined by the cur- rent-sense voltages: i fb = g m(fb) x (v csp - v csn ) where v csp - v csn is the differential current-sense volt- age, and g m(fb) is typically 600s, as defined in the electrical characteristics table. differential remote sense the MAX17409 includes differential, remote-sense inputs to eliminate the effects of voltage drops along the pcb traces and through the processors power pins. the feedback-sense node connects to the voltage-posi- tioning resistor (r fb ). the ground-sense (gnds) input connects to an amplifier that adds an offset directly to the target voltage, effectively adjusting the output volt- age to counteract the voltage drop in the ground path. connect the voltage-positioning resistor (r fb ) and ground-sense (gnds) input directly to the processors remote-sense outputs as shown in figure 1. integrator amplifier an integrator amplifier forces the dc average of the fb voltage to equal the target voltage. this transconduc- tance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage vv ri out target fb fb = - MAX17409 1-phase quick-pwm nvidia cpu controller ______________________________________________________________________________________ 19 (figure 2), allowing accurate dc output-voltage regula- tion regardless of the output ripple voltage. the integra- tor amplifier has the ability to shift the output voltage by 80mv (typ). the differential input voltage range is at least 60mv total, including dc offset and ac ripple. the integration time constant can be set easily with an external compensation capacitor between ccv and analog ground, with the minimum recommended ccv capacitor value determined by: where g m(ccv) is the integrators maximum transcon- ductance (320s) and f sw is the switching frequency set by the ton resistance. the MAX17409 disables the integrator by connecting the amplifier inputs together at the beginning of all vid transitions done in pulse-skipping mode (skip = high). the integrator remains disabled until 20s after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator). nominal output-voltage selection the nominal no-load output voltage (v target ) is defined by the selected voltage reference (vid dac) plus the remote ground-sense adjustment (v gnds ) as defined in the following equation: where v dac is the selected vid voltage. on startup, the MAX17409 slews the target voltage from ground to the selected vid voltage. dac inputs (g0?5) the digital-to-analog converter (dac) programs the output voltage using the g0Cg5 inputs. g0Cg5 are low- voltage (1.0v) logic inputs, designed to interface direct- ly with the cpu. do not leave g0Cg5 unconnected. changing g0Cg5 initiates a transition to a new output- voltage level. change g0Cg5 together, avoiding greater than 20ns skew between bits. otherwise, incor- rect dac readings could cause a partial transition to the wrong voltage level followed by the intended transi- tion to the correct voltage level, lengthening the overall transition time (table 4). vvvv target fb dac gnds == + c g f ccv m ccv sw >> () 16 shdn skip operating mode description gnd x disabled low-power shutdown mode. dl forced low, and the controller is disabled. the supply current drops to 10a (max). rising x pulse-skipping 1.56mv/s slew rate startup. when shdn is pulled high, the MAX17409 begins the startup sequence. the controller enables the pwm controller and ramps the output voltage up to the selected vid voltage. high low forced-pwm 12.5mv/s slew rate full power. the no-load output voltage is determined by the selected vid dac code (g0Cg5, table 4). high high pulse-skipping 12.5mv/s slew rate suspend mode. the no-load output voltage is determined by the selected vid dac code (g0Cg5, table 4). when skip is pulled high, the MAX17409 immediately enters pulse-skipping operation, allowing automatic pwm/pfm switchover under light loads. the pwrgd upper threshold is blanked during the transition. falling x forced-pwm 1.56mv/s slew rate shutdown. when shdn is pulled low, the MAX17409 immediately pulls pwrgd low, and the output voltage is ramped down to ground. once the output reaches 0v, the controller enters the low-power shutdown state. high x disabled fault mode. the fault latch has been set by the MAX17409 uvp or thermal-shutdown protection, or by the ovp protection. the controller remains in fault mode until v cc power is cycled or shdn toggled. table 3. MAX17409 operating mode truth table MAX17409 1-phase quick-pwm nvidia cpu controller 20 ______________________________________________________________________________________ g5 g4 g3 g2 g1 g0 output voltage (v) 1 0 0 0 0 0 1.1250 1 0 0 0 0 1 1.1125 1 0 0 0 1 0 1.1000 1 0 0 0 1 1 1.0875 1 0 0 1 0 0 1.0750 1 0 0 1 0 1 1.0675 1 0 0 1 1 0 1.0500 1 0 0 1 1 1 1.0375 1 0 1 0 0 0 1.0250 1 0 1 0 0 1 1.0125 1 0 1 0 1 0 1.0000 1 0 1 0 1 1 0.9875 1 0 1 1 0 0 0.9750 1 0 1 1 0 1 0.9625 1 0 1 1 1 0 0.9500 1 0 1 1 1 1 0.9275 1 1 0 0 0 0 0.9250 1 1 0 0 0 1 0.9125 1 1 0 0 1 0 0.9000 1 1 0 0 1 1 0.8875 1 1 0 1 0 0 0.8750 1 1 0 1 0 1 0.8625 1 1 0 1 1 0 0.8500 1 1 0 1 1 1 0.8375 1 1 1 0 0 0 0.8250 1 1 1 0 0 1 0.8125 1 1 1 0 1 0 0.8000 1 1 1 0 1 1 0.7875 1 1 1 1 0 0 0.7750 1 1 1 1 0 1 0.7625 1 1 1 1 1 0 0.7500 1 1 1 1 1 1 0.7375 g5 g4 g3 g2 g1 g0 output voltage (v) 0 0 0 0 0 0 0.7250 0 0 0 0 0 1 0.7125 0 0 0 0 1 0 0.7000 0 0 0 0 1 1 0.6875 0 0 0 1 0 0 0.6750 0 0 0 1 0 1 0.6625 0 0 0 1 1 0 0.6500 0 0 0 1 1 1 0.6275 0 0 1 0 0 0 0.6250 0 0 1 0 0 1 0.6125 0 0 1 0 1 0 0.6000 0 0 1 0 1 1 0.5875 0 0 1 1 0 0 0.5750 0 0 1 1 0 1 0.5625 0 0 1 1 1 0 0.5500 0 0 1 1 1 1 0.5275 0 1 0 0 0 0 0.5250 0 1 0 0 0 1 0.5125 0 1 0 0 1 0 0.5000 0 1 0 0 1 1 0.4875 0 1 0 1 0 0 0.4750 0 1 0 1 0 1 0.4625 0 1 0 1 1 0 0.4500 0 1 0 1 1 1 0.4275 0 1 1 0 0 0 0.4250 0 1 1 0 0 1 0.4125 0 1 1 0 1 0 0.4000 0 1 1 0 1 1 0.3875 0 1 1 1 0 0 0.3750 0 1 1 1 0 1 0.3625 0 1 1 1 1 0 0.3500 0 1 1 1 1 1 0.3375 table 4. output voltage vid dac codes MAX17409 1-phase quick-pwm nvidia cpu controller ______________________________________________________________________________________ 21 output-voltage transition timing the MAX17409 performs mode transitions in a controlled manner, automatically minimizing input surge currents. this feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a given output capacitance. at the beginning of an output-voltage transition, the MAX17409 blanks both pwrgd thresholds, preventing the pwrgd open-drain output from changing states during the transition. the controller enables the pwrgd thresholds approximately 20s after the slew- rate controller reaches the target output voltage. the slew rate is set to 12.5mv/s to ensure that the transi- tion can be completed within a reasonable time period. the MAX17409 automatically controls the current to the minimum level required to complete the transition in the calculated time. the slew-rate controller uses an inter- nal capacitor and current source to transition the target voltage. the total transition time depends on the 12.5mv/s slew rate, the voltage difference, and the accuracy of the slew-rate controller, c slew , accuracy). the slew rate is not dependent on the total output capacitance, as long as the surge current is less than the current limit. for all dynamic vid transitions, the transition time (t tran ) is given by: where v old is the original output voltage, and v new is the new target voltage. see slew-rate accuracy in the electrical characteristics for slew-rate limits. for soft- start and shutdown, the controller automatically reduces the slew rate to 1.56mv/s (1/8 of the nominal slew rate). the output voltage tracks the slewed target voltage, making the transitions relatively smooth. the average inductor current required to make an output voltage transition is: where c out is the total output capacitance. ic mvs lout ? 12 5 . t vv mvs tran new old = - 12 5 . skip pwrgd internal pwm control blank high-z pulse-skipping mode dh ovp level cpu core voltage internal target actual v out blank high-z vid (g0?g5) low threshold only forced-pwm mode new active vid low vid high vid ovp = 1.45v min no pulses: v out > v target t blank 20 figure 4. vid transition MAX17409 1-phase quick-pwm nvidia cpu controller 22 ______________________________________________________________________________________ forced-pwm operation (normal mode) during soft-shutdown and normal operationwhen the cpu is actively running (skip = low, table 3) the MAX17409 operates with the low-noise, forced-pwm control scheme. forced-pwm operation disables the zero-crossing comparator, forcing the low-side gate- drive waveforms to constantly be the complement of the high-side gate-drive waveforms. this keeps the switching frequency constant and allows the inductor current to reverse under light loads, providing fast, accurate negative-output-voltage transitions by quickly discharging the output capacitors. forced-pwm operation comes at a cost: the no-load +5v bias supply current remains between 10ma to 50ma, depending on the external mosfets and switching frequency. to maintain high efficiency under light-load conditions, the processor might switch the controller to a low-power pulse-skipping control scheme after entering suspend mode. the MAX17409 automatically uses pulse-skipping operation during soft-start, regardless of the skip configuration. light-load pulse-skipping operation during soft-start and sleep statesskip is pulled highthe MAX17409 operates in pulse-skipping mode. the pulse-skipping mode enables the drivers zero- crossing comparator, so the controller pulls dl low when its current-sense inputs detect zero inductor current. this keeps the inductor from sinking current and discharging the output capacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging the output. upon entering pulse-skipping operation, the controller temporarily blanks the upper pwrgd thresholds, and sets the ovp threshold to 1.80v to prevent false ovp faults when the transition to pulse-skipping operation coincides with a vid dac code. the MAX17409 auto- matically uses forced-pwm operation during soft-shut- down, regardless of the skip configuration. automatic pulse-skipping switchover in skip mode (skip = high), an inherent automatic switchover to pfm takes place at light loads. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor currents zero crossing. the zero-crossing comparator senses the inductor current across the low-side mosfets. once v lx drops below the zero-crossing comparator threshold (see the electrical characteristics table), the comparator forces dl low (figure 2). this mechanism causes the threshold between pulse-skipping pfm and nonskipping-pwm operation to coincide with the boundary between continuous and discontinuous induc- tor-current operation. the pfm/pwm crossover occurs when the load current is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (figure 5). for a 7v to 20v battery input range, this threshold is relatively constant, with only a minor depen- dence on the input voltage due to the typically low duty cycles. the total load current at the pfm/pwm crossover threshold (i load(skip) ) is approximately: the switching waveforms might appear noisy and asyn- chronous when light loading activates pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs between pfm noise and light-load efficiency are made by varying the inductor value. generally, low inductor values pro- duce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output volt- age ripple. penalties for using higher inductor values include larger physical size and degraded load-tran- sient response, especially at low input-voltage levels. i tv l vv v load skip sw out in out in () = ? ? ? ? ? ? ? ? ? ? 1 2 - ? ? ? inductor current i load = i peak /2 on-time 0 time i peak l v batt - v out i t = figure 5. pulse-skipping/discontinuous crossover point MAX17409 1-phase quick-pwm nvidia cpu controller ______________________________________________________________________________________ 23 power-up sequence (por, uvlo) the MAX17409 is enabled when shdn is driven high (figure 6). the reference powers up first. once the ref- erence exceeds its uvlo threshold, the internal analog blocks are turned on and masked by a 150s one-shot delay. the pwm controller then begins switching. power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and prepar- ing the controller for operation. the v cc uvlo circuitry inhibits switching until v cc rises above 4.25v. the con- troller powers up the reference once the system enables the controller, v cc is above 4.25v, and shdn is driven high. with the reference in regulation, the con- troller ramps the output voltage to the selected vid volt- age with a 1.56mv/s slew rate: where v boot is the initial vid target. the soft-start cir- cuitry does not use a variable current limit, so full output current is available immediately. pwrgd becomes high impedance approximately 5ms after the target out- put voltage is reached. the MAX17409 automatically uses pulse-skipping mode during soft-start and uses forced-pwm mode during soft-shutdown, regardless of the skip configuration. for automatic startup, the battery voltage should be present before v cc . if the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. the controller remains shut down until the fault latch is cleared by toggling shdn or cycling the v cc power supply below 0.5v. if the v cc voltage drops below 4.25v, the controller assumes that there is not enough supply voltage to make valid decisions. to protect the output from over- voltage faults, the controller shuts down immediately and forces a high-impedance output (dl and dh pulled low). t v mv s tran start boot () ./ = () 156 pwrgd internal pwm control ovp level v cc g0?g5 t blank 60 s typ t blank 20 s slew rate soft-shutdown = 1.56mv/ s slew rate pulse skipping initial target v core ovp = 1.45v min ovp = 1.45v min figure 6. power-up and shutdown sequence timing diagram MAX17409 1-phase quick-pwm nvidia cpu controller 24 ______________________________________________________________________________________ shutdown when shdn goes low, the MAX17409 enters low-power shutdown mode. pwrgd is pulled low immediately, and the output voltage ramps down with a 1.56mv/s slew rate: slowly discharging the output capacitors by slewing the output over a long period of time keeps the average negative inductor current low (damped response), thereby eliminating the negative output-voltage excur- sion that occurs when the controller discharges the out- put quickly by permanently turning on the low-side mosfet (underdamped response). this eliminates the need for the schottky diode normally connected between the output and ground to clamp the negative output-voltage excursion. after the controller reaches the zero target, the MAX17409 shuts down completely the drivers are disabled (dl driven high, dh pulled low)the reference turns off, and the supply currents drop to approximately 1a (max). when a fault conditionoutput uvlo or thermal shut- downactivates the shutdown sequence, the protec- tion circuitry sets the fault latch to prevent the controller from restarting. to clear the fault latch and reactivate the controller, toggle shdn or cycle v cc power below 0.5v typ. temperature comparator ( vrhot ) the MAX17409 also features an independent compara- tor with an accurate threshold (v hot ) that tracks the analog supply voltage (v hot = 0.3v cc ). this makes the thermal trip threshold independent of the v cc supply voltage tolerance. use a resistor- and thermistor-divider between v cc and gnd to generate a voltage-regulator overtemperature monitor. place the thermistor as close to the mosfets and inductors as possible. fault protection (latched) output overvoltage (ovp) protection the ovp circuit is designed to protect the processor against a shorted high-side mosfet by drawing high current and blowing the battery fuse. the MAX17409 continuously monitors the output for an overvoltage fault. the controller detects an ovp fault if the output voltage exceeds the set vid dac voltage by more than 300mv, subject to a minimum ovp threshold of 0.8v. during pulse-skipping operation (skip = high), the controller initially sets the ovp threshold to a fixed 1.8v threshold. once the output is in regulation (the first on-time is trig- gered) and the pwrgd blanking time expires, the con- troller tightens the ovp threshold, tracking the ovp threshold by 300mv, subject to a minimum ovp thresh- old of 0.8v. the controller also uses the fixed 1.8v ovp threshold during soft-start and soft-shutdown. when the ovp circuit detects an overvoltage fault, the MAX17409 immediately forces dl high and pulls dh low. this action turns on the synchronous-rectifier mosfets with 100% duty and, in turn, rapidly discharges the output filter capacitor and forces the output low. if the condition that caused the overvoltage (such as a shorted high-side mosfet) persists, the battery fuse blows. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller. ovp protection can be disabled through the no-fault test mode (see the no-fault test mode section). output undervoltage protection (uvp) the output uvp function is similar to foldback current limiting, but employs a timer rather than a variable cur- rent limit. if the MAX17409 output voltage is 400mv below the target voltage, the controller activates the shutdown sequence and sets the fault latch. once the controller ramps down to zero, it forces the dl high, and pulls dh low. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller. uvp protection can be disabled through the no-fault test mode (see the no-fault test mode section). thermal-fault protection the MAX17409 features a thermal-fault protection cir- cuit. when the junction temperature rises above +160c, an internal thermal sensor sets the fault latch and forces the dl high and the dh low. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller after the junction temperature cools by 15c. thermal shutdown can be disabled through the no-fault test mode (see the no- fault test mode section). no-fault test mode the latched fault protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to deter- mine what went wrong. therefore, a no-fault test mode is provided to disable the fault protectionover- voltage protection, undervoltage protection, and ther- mal shutdown. additionally, the test mode clears the fault latch if it has been set. the no-fault test mode is entered by forcing 11v to 13v on shdn . t v mv s tran shdn out () ./ = () 156 MAX17409 1-phase quick-pwm nvidia cpu controller ______________________________________________________________________________________ 25 mosfet gate drivers the dh and dl drivers are optimized for driving moder- ate-sized high-side and larger low-side power mosfets. this is consistent with the low duty factor seen in notebook applications, where a large v in - v out differential exists. the high-side gate drivers (dh) source and sink 2.2a, and the low-side gate drivers (dl) source 2.7a and sink 8a. this ensures robust gate drive for high-current applications. the dh floating high-side mosfet drivers are powered by internal boost switch charge pumps at bst, while the dl syn- chronous-rectifier drivers are powered directly by the 5v bias supply (v dd ). adaptive dead-time circuits monitor the dl and dh dri- vers and prevent either fet from turning on until the other is fully off. the adaptive driver dead-time allows operation without shoot-through with a wide range of mosfets, minimizing delays and maintaining efficiency. there must be a low-resistance, low-inductance path from the dl and dh drivers to the mosfet gates for the adaptive dead-time circuits to work properly; other- wise, the sense circuitry in the MAX17409 interprets the mosfet gates as off while charge actually remains. use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). the internal pulldown transistor that drives dl low is robust, with a 0.25 (typ) on-resistance. this helps dl from being pulled up due to capacitive coupling from the drain to the gate of the low-side mosfets when the inductor node (lx) quickly switches from ground to v in . applications with high input voltages and long inductive driver traces might require that rising lx edges do not pull up the low-side mosfets gate, causing shoot- through currents. the capacitive coupling between lx and dl created by the mosfets gate-to-drain capaci- tance (c rss ), gate-to-source capacitance (c iss - c rss ), and additional board parasitics should not exceed the following minimum threshold: typically, adding a 4700pf between dl and power ground (c nl in figure 7), close to the low-side mosfets, greatly reduces coupling. do not exceed 22nf of total gate capacitance to prevent excessive turn-off delays. alternatively, shoot-through currents could be caused by a combination of fast high-side mosfets and slow low-side mosfets. if the turn-off delay time of the low- side mosfet is too long, the high-side mosfets can turn on before the low-side mosfets have actually turned off. adding a resistor less than 5 in series with bst slows down the high-side mosfet turn-on time, eliminating the shoot-through currents without degrad- ing the turn-off time (r bst in figure 7). slowing down the high-side mosfet also reduces the lx node rise time, thereby reducing emi and high-frequency cou- pling responsible for switching noise. quick-pwm design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: input voltage range: the maximum value (v in(max) ) must accommodate the worst-case high ac adapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selec- tor switches. if there is a choice at all, lower input voltages result in better efficiency. maximum load current: there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and filtering requirements, and thus drives output vv c c gs th in rss iss () > ? ? ? ? ? ? bst dh lx input (v in ) n h c bst (c nl )* c byp (r bst )* n l l (r bst )* optional?the resistor lowers emi, decreasing the switching node rise time. (c nl )* optional?the capacitor reduces lx to dl capacitive coupling that can cause shoot-through currents. dl pgnd v dd MAX17409 figure 7. gate-drive circuit MAX17409 1-phase quick-pwm nvidia cpu controller 26 ______________________________________________________________________________________ capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continu- ous load current (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-con- tributing components. modern notebook cpus gen- erally exhibit i load = i load(max) x 80%. switching frequency: this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are proportional to frequency and v in 2 . the opti- mum frequency is also a moving target, due to rapid improvements in mosfet technology that are making higher frequencies more practical. inductor operating point: this choice provides trade-offs between size vs. efficiency and transient response vs. output noise. low inductor values pro- vide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduc- tion (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction bene- fit. the optimum operating point is usually found between 20% and 50% ripple current. inductor selection the switching frequency and operating point (% ripple current or lir) determine the inductor value as follows: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite and molded iron cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): transient response the inductor ripple current impacts transient-response performance, especially at low v in - v out differentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output fil- ter capacitors by a sudden load step. the amount of output sag is also a function of the maximum duty fac- tor, which can be calculated from the on-time and mini- mum off-time. the worst-case output sag voltage can be determined by: where t off(min) is the minimum off-time (see the electrical characteristics table). the amount of overshoot due to stored inductor energy can be calculated as: current-limit control (ilim) ref and ilim are used to set the current limit. ref reg- ulates to a fixed 2.0v and the ref-to-ilim voltage determines the valley current-sense threshold. when ilim = v cc , the controller uses the preset 22.5mv cur- rent-limit threshold. in an adjustable design, ilim is connected to a resistive voltage-divider connected between ref and ground. the differential voltage between ref and ilim sets the current-limit threshold (v limit ), so the valley current-sense threshold is: this allows design flexibility since the dcr sense circuit or sense resistor does not have to be adjusted to meet the current limit as long as the current-sense voltage never exceeds 50mv. keeping v limit between 20mv to 40mv leaves room for future current-limit adjustment. the minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half the ripple current; therefore: ii lir valley load max > ? ? ? ? ? ? () 1 2 - v vv limit ref ilim = - 10 v il cv soar load max out out () () 2 2 v vt v t sag out sw in off = () ? ? ? ? ? ? + li load(max) 2 ( m min out out in out sw in cv vv t v ) ? ? ? ? ? ? () ? ? ? ? ? ? 2 - - t t off min () ? ? ? ? ? ? ? ? ii lir peak load max =+ ? ? ? ? ? ? () 1 2 l vv fi lir v v in out sw load max out in = ? ? ? ? ? ? ? ? ? ? - () ? ? ? MAX17409 1-phase quick-pwm nvidia cpu controller ______________________________________________________________________________________ 27 where: where r sense is the sensing resistor and r csp-csn / r lx-csn is the ratio of resistor-divider with dcr-sensing approach. voltage positioning and loop compensation voltage positioning dynamically lowers the output volt- age in response to the load current, reducing the out- put capacitance and processors power dissipation requirements. the controller uses a transconductance amplifier to set the transient and dc output voltage droop (figure 2) as a function of the load. this adjusta- bility allows flexibility in the selected current-sense resistor value or inductor dcr, and allows smaller cur- rent-sense resistance to be used, reducing the overall power dissipated. steady-state voltage positioning connect a resistor (r fb ) between fb and v out to set the dc steady-state droop (load line) based on the required voltage positioning slope (r droop ): where the effective current-sense resistance (r sense ) depends on the current-sense method (see the current sense section), and the voltage-positioning amplifiers transconductance (g m(fb) ) is typically 600s as defined in the electrical characteristics table. when the inductors dcr is used as the current-sense element (r sense = r dcr ), each current-sense input should include an ntc thermistor to minimize the temperature dependence of the voltage-positioning slope. output capacitor selection the output filter capacitor must have low enough effec- tive equivalent series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. in processor core supplies and other applications where the output is subject to large load transients, the output capacitors size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in nonprocessor applications, the output capacitors size often depends on how much esr is needed to maintain an acceptable level of output ripple voltage. the output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitors esr. the maximum esr to meet rip- ple requirements is: where f sw is the switching frequency. the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usu- ally selected by esr and voltage rating rather than by capacitance value (this is true of polymer types). when using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equations in the transient response section). output capacitor stability considerations for quick-pwm controllers, stability is determined by the value of the esr zero relative to the switching fre- quency. the boundary of instability is given by the fol- lowing equation: where: and: where c out is the total output capacitance, r esr is the total esr, r sense is the current-sense resistance (r cm = r cs ), r droop(ac) is the ac component of the droop, and r pcb is the parasitic board resistance between the output capacitors and sense resistors. rrr r eff esr droop ac pcb =+ + () f rc esr eff out = 1 2 f f esr sw r vf l vv v v esr in sw in out out ripple () ? ? ? ? ? ? ? ? - rr v i esr pcb step load max + () () r r rg fb droop sense m fb = () i v r v dcr r r valley limit sense limit csp csn lx == - - c csn MAX17409 1-phase quick-pwm nvidia cpu controller 28 ______________________________________________________________________________________ in applications that require dc droop, r droop(ac) is the same as the dc droop setting (r droop(ac) = r droop(dc) ). in applications that do not require dc droop, this ac signal is generated by capacitively cou- pling the inductor ripple current signal to the fb pin. in this case, r droop(ac) = r sense , where r sense is the effective sense resistance seen at the csp-csn pins. in figure 1, c3 couples the inductor ripple current signal to the fb pin. c3 can be connected to the csn pin or the csp pin. connecting to the csn pin only couples the out- put capacitor esr to the fb pin. connecting to the csp pin adds the r sense component to the effective resis- tance in addition to the output capacitor esr. this is use- ful for applications using all ceramic output capacitors. keep the c3 x r fb time constant between 3x and 5x of the switching period. practical values for c3 range from 0.1f to 1f. calculate r fb after selecting c3. keeping r fb below 100 minimizes any residual dc droop. in the standard application circuit (figure 1), the effec- tive resistance for stability is the sum of the ~ 2m dcr and the 6m esr of the 470f output capacitor. the esr zero frequency is 42khz, well within the require- ment of f sw / . ceramic capacitors have a high-esr zero frequency, but applications with significant voltage positioning can take advantage of their size and low esr. do not put high-value ceramic capacitors directly across the out- put without verifying that the circuit contains enough voltage positioning and series pcb resistance to ensure stability. when only using ceramic output capacitors, output overshoot (v soar ) typically deter- mines the minimum output capacitance requirement. their relatively low capacitance value can cause output overshoot when stepping from full-load to no-load con- ditions, unless a small inductor value is used (high switching frequency) to minimize the energy transferred from inductor to capacitor during load-step recovery. unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feedback loop instability. double-pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output-voltage signal. this fools the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability can result in oscillations at the output after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. the i rms requirements can be determined by the fol- lowing equation: the worst-case rms current requirement occurs when operating with v in = 2v out . at this point, the above equation simplifies to i rms = 0.5 x i load . for most applications, nontantalum chemistries (ceram- ic, aluminum, or os-con) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. if the quick-pwm controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. in either con- figuration, choose an input capacitor that exhibits less than +10 c temperature rise at the rms input current for optimal circuit longevity. power-mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20v) ac adapters. low- current applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . calculate both of these sums. ideally, the losses at v in(min) should be roughly equal to losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher than the losses at v in(max) , consider increasing the size of n h (reducing r ds(on) but with higher c gate ). conversely, if the losses at v in(max) are significantly higher than the losses at v in(min) , consider reducing the size of n h (increasing r ds(on) to lower c gate ). if v in does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. choose a low-side mosfet that has the lowest possible on-resistance (r ds(on) ), comes in a moderate-sized package (i.e., one or two 8-pin sos, dpak, or d 2 pak), and is reasonably priced. make sure that the dl gate i i v vvv rms load in out in out = ? ? ? ? ? ? () - MAX17409 1-phase quick-pwm nvidia cpu controller ______________________________________________________________________________________ 29 driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate- to-drain capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction problems could occur (see the mosfet gate drivers section). mosfet power dissipation worst-case conduction losses occur in the high-side mosfet (n h ) is a function of the duty factor, with the worst-case power dissipation occurring at the minimum input voltage: generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power dissipation often limits how small the mosfet can be. again, the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high- side switching losses do not usually become an issue until the input is greater than approximately 15v. calculating the switching losses in a high-side mosfet (n h ) is difficult since it must allow for difficult quantify- ing factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pcb layout characteristics. the following switching-loss cal- culation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably includ- ing verification using a thermocouple mounted on n h : where c oss is the n h mosfets output capacitance, q g(sw) is the charge needed to turn on the n h mosfet, and i gate is the peak gate-drive source/sink current (2.2a typ). switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the c x v in 2 x f sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when biased from v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum input voltage: the worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) , but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro- tect against this possibility, the circuit can be overde- signed to tolerate: where i valley(max) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. the mosfets must have a good size heatsink to handle the overload power dissipation. choose a schottky diode (d l ) with a forward voltage low enough to prevent the low-side mosfet body diode from turning on during the dead time. select a diode that can handle the load current during the dead times. this diode is optional and can be removed if effi- ciency is not critical. boost capacitors the boost capacitors (c bst ) must be selected large enough to handle the gate charging requirements of the high-side mosfets. however, high-current appli- cations driving large high-side mosfets require boost capacitors larger than 0.1f. for these applications, select the boost capacitors to avoid discharging the capacitor more than 200mv while charging the high- side mosfets gates: where n is the number of high-side mosfets used for one regulator, and q gate is the gate charge specified in the mosfets data sheet. for example, assume (2) irf7811w n-channel mosfets are used on the high side. according to the manufacturers data sheet, a sin- gle irf7811w has a maximum gate charge of 24nc (v gs = 5v). using the above equation, the required boost capacitance would be: selecting the closest standard value, this example requires a 0.22f ceramic capacitor. c nc mv f bst = = 224 200 024 . c nq mv bst gate = 200 ii i load valley max inductor =+ ? ? ? ? ? ? () 2 () () =+ ? ? ? ? ? ? i ilir valley max load max 2 pd (nl resistive) = 1 - v v out in max () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () ir load ds on 2 () pd (nh switching) = v i f q i in load sw gsw gate () ? ? ? ? ? ? ? + cv oss in 2 2 2 f sw pd (nh resistive) = v v ir out in load ds ? ? ? ? ? ? 2 (o on) MAX17409 1-phase quick-pwm nvidia cpu controller 30 ______________________________________________________________________________________ applications information positive offset some applications require a positive offset to shift the output voltage to a different level. this might be neces- sary to obtain a voltage not supported by the vid code, or to allow a shift in the vid code mapping. a positive offset is generated by raising the voltage at the gnds/ofsp pin using a resistor-divider from ref. refer to r14 and r20 in figure 1. the voltage at the gnds/ofsp pin relative to the analog ground of the ic sets the offset voltage that is added to the programmed vid voltage: and: v target = v dac + v offset pcb layout guidelines careful pcb layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention (figure 8). if possible, mount all the power components on the top side of the board with their ground terminals flush against one another. follow the MAX17409 evaluation kit layout and use the following guidelines for good pcb layout: ? keep the high-current paths short, especially at the ground terminals. this is essential for stable, jitter- free operation. ? connect all analog grounds to a separate solid cop- per plane, which connects to the gnd pin of the quick-pwm controller. this includes the v cc bypass capacitor, ref, gnds bypass capacitors, and compensation (ccv) components. ? keep the power traces and load connections short. this is essential for high efficiency. the use of thick copper pcbs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a mea- surable efficiency penalty. ? keep the high-current, gate-driver traces (dl, dh, lx, and bst) short and wide to minimize trace resistance and inductance. this is essential for high-power mosfets that require low-impedance gate drivers to avoid shoot-through currents. ? csp and csn connections for current limiting and voltage positioning must be made using kelvin-sense connections to guarantee the current-sense accuracy. ? when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. ? route high-speed switching nodes away from sen- sitive analog areas (ccv, fb, csp, csn, etc.). layout procedures 1) place the power components first, with ground ter- minals adjacent (low-side mosfet source, c in , c out , and d1 anode). if possible, make all these connections on the top layer with wide, copper- filled areas. 2) mount the controller ic adjacent to the low-side mosfet. the dl gate traces must be short and wide (50mils to 100mils wide if the mosfet is 1in from the controller ic). 3) group the gate-drive components (bst capacitors, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figure 1. this diagram can be viewed as having four separate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the pgnd pin and v dd bypass capacitor go; the masters analog ground plane where sensitive analog components go, the masters gnd pin and v cc bypass capaci- tor go; and the slaves analog ground plane where the slaves gnd pin and v cc bypass capacitor go. the masters gnd plane must meet the pgnd plane only at a single point directly beneath the ic. similarly, the slaves gnd plane must meet the pgnd plane only at a single point directly beneath the ic. the respective master and slave ground planes should connect to the high-power output ground with a short metal trace from pgnd to the source of the low-side mosfet (the middle of the star ground). this point must also be very close to the output capacitor ground terminal. 5) connect the output power planes (v core and sys- tem ground planes) directly to the output filter capacitor positive and negative terminals with multi- ple vias. place the entire dc-dc converter circuit as close to the cpu as is practical. vv r rr v gnds offset ref == + ? ? ? ? ? ? 14 20 14 MAX17409 1-phase quick-pwm nvidia cpu controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 31 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 28 tqfn t2844-1 21-0139 chip information process: bicmos kelvin sense vias under the inductor (see MAX17409 evaluation kit) kelvin sense vias to inductor pad power ground power stage layout (top side of pcb) inductor dcr sensing inductor l csp csn r ntc r2 r1 c eq c out c out c in1 input smps output figure 8. pcb layout example |
Price & Availability of MAX17409
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |